Method for selective under-etching of porous silicon

ABSTRACT

A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. patent applicationSer. No. 12/716,785, filed Mar. 3, 2010, which claims priority under 35U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No.61/157,195, filed on Mar. 3, 2009, and titled “METHOD FOR SELECTIVEUNDER-ETCHING OF POROUS SILICON,” the entirety of which is herebyincorporated by reference.

FIELD OF THE INVENTION

This invention relates to a method for making solar cells. Moreparticularly, the present invention relates to selective etching of aporous silicon layer to under-cut and release a silicon-based devicelayer that is then used for making solar cells.

BACKGROUND OF THE INVENTION

Solar cells are semiconductor devices that are usually manufactured fromsilicon-based material. Some solar cells are made from screen printedpoly-crystalline silicon. Single crystalline wafers can be used to makevery efficient solar cells. However, high manufacturing costs for makingsingle crystalline materials makes the large scale production of solarcells from these materials impractical.

Poly-crystalline silicon wafers used to manufacture solar cells are madeby cutting 180 to 350 micrometer thick wafers from block-cast siliconingots. The wafers are usually lightly p-type doped. To make a solarcell from the wafer, a surface diffusion of n-type dopants is performedon the front side of the wafer. This forms a p-n junction a few hundrednanometers below the surface. Solar cells usually also includeanti-reflective coatings, such as silicon nitride or titanium dioxideand/or have textured surfaces increase efficiency of light absorption.This method is disadvantageous in that the crystal takes anexceptionally long time to grow on the silicon ingot.

Metal contacts are formed on the back and front surfaces ofpoly-crystalline silicon wafers by screen-printing metal pastes, such assilver paste or aluminum paste. After the metal contacts are formed, thesolar cells are assembled into panels and are sandwiched between glassand polymer resins.

As mentioned above, solar cells and solar panels that are formed fromsingle crystal silicon are preferred because of the efficiency of thesolar cells and panels made from single crystal silicon.

SUMMARY OF THE INVENTION

The present invention is direct to a method of making a solar cell. Inaccordance with the method of the present invention, a silicon-baseddevice layer is formed on a base wafer. The base wafer includes a singlecrystal silicon wafer and a sacrificial porous silicon layer that isdeposited thereon. The sacrificial porous silicon layer is formed usingthermal deposition or any other suitable coating or depositiontechnique. Preferably, the porous silicon layer has a porosity of 30percent or more. The sacrificial porous silicon layer comprises, forexample, carbon doped oxide, spin-on-glass (SOG), fluoridated siliconglass (FSG) or a combination thereof. The thickness of the poroussilicon layer is preferably in a range of several nanometers to severalmicrons.

The silicon-based device layer is preferably crystalline orsemi-crystalline, as opposed to being amorphous, and is epitaxiallygrown on top of the sacrificial porous silicon layer. The silicon-baseddevice layer is preferably a p-doped silicon-based device layer that hasa thickness of several microns to several hundred microns. Thesilicon-based device layer is formed using any suitable growth ordeposition technique, such as chemical vapor deposition. A working waferthat includes the single crystal silicon wafer, the silicon-based devicelayer and the sacrificial porous silicon layer sandwiched between thesingle crystal silicon wafer and the silicon-based device layer isreferred to herein as a composited wafer.

In accordance with the embodiments of the invention, after the compositewafer is formed the sacrificial layer is selectively etched therebyreleasing the silicon-based device layer, or a portion thereof and thesingle crystal wafer, or a portion thereof. The released silicon-baseddevice layer, or the portion thereof, is then provided with theappropriate electrical contacts and anti-reflective coatings and iscoupled to one or more substrates to form a solar cell. The releasedsingle crystal wafer, or the portion thereof, is then used to makeadditional composite wafers and additional solar cells, such asdescribed above.

In order to accomplish release of the silicon-based device layer, or theportion thereof, the etch rate of the porous silicon layer needs to besignificantly faster than the etch rates of either the single crystalwafer or of the silicon-based device layer. Selective etching of thesacrificial porous silicon layer has been observed by treating thecomposite wafer to an aqueous etchant that is maintained at temperaturesin a range of 0 to 10 degrees Celsius. The aqueous etchant preferablyincludes one or more etchants such as potassium hydroxide, sodiumhydroxide and hydrogen fluoride in a concentration of 5% or less byweight. In further embodiments of the invention the aqueous etchantincludes an alcohol, such as isopropyl alcohol, in a concentration of10% or less by weight. In still further embodiments of the invention theetchant includes a surfactant in a concentration of 1% or less byweight. Also, to further control etch rates during the selective etchingstep, the composite wafer and the aqueous etchant are treated withultrasonic energy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a composite wafer used to make a silicon-based devicelayer for solar cells, in accordance with the embodiments of theinvention.

FIG. 1B illustrates releasing a silicon-based device layer from thecomposite wafer, in accordance with the embodiments of the invention.

FIG. 1C shows a released silicon-based device layer coupled to asubstrate to form a solar cell, in accordance with the embodiments ofthe invention.

FIG. 2A shows a block-flow diagram outlining steps for making a solarcell, in accordance with the method of the invention.

FIG. 2B shows a block-flow diagram outlining steps for making acomposite wafer, in accordance with the method of the invention.

FIG. 2C shows a block-flow diagram outlining steps for releasing adevice layer from the composite wafer, in accordance with the method ofthe invention.

FIG. 3 shows a schematic representation of a solar panel with multiplesolar cells on a common substrate, in accordance with the embodiments ofthe invention.

FIG. 4 shows a schematic representation of a system that utilizes asolar cell or panel, in accordance with the embodiments of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a composite wafer 100 used to make a silicon-based devicelayer used in solar cells. The composite wafer 100 includes a singlecrystal silicon wafer 101 and a sacrificial porous silicon layer 103that is deposited thereon, which is referred to herein as a base wafer.The composite wafer 100 also includes a silicon-based device layer 105that is preferably crystalline or semi-crystalline and is epitaxiallygrown on top of the sacrificial porous silicon layer 103.

As described above, the sacrificial porous silicon layer 103 preferablyhas a porosity of 30 percent or more and is several nanometers toseveral microns thick. The sacrificial porous silicon layer 103 isformed from any suitable porous silicon material including, but notlimited to carbon doped oxide, spin-on-glass (SOG), fluoridated siliconglass (FSG) or a combination thereof.

The silicon-based device layer 105 is preferably a p-doped silicon-baseddevice layer that has a thickness of several microns to several hundredmicrons. The sacrificial porous silicon layer 103 and the silicon-baseddevice layer 105 are formed using any suitable coating, growth and/ordeposition techniques including, but not limited to, thermal depositionand chemical vapor deposition.

FIG. 1B illustrates a schematic representation 120 of a releasedsilicon-based device layer 105′ and a released single crystal siliconwafer 101′ which are formed by selectively etching the sacrificialporous silicon layer 103, as indicated by the arrow 109. Selectiveetching of the sacrificial porous silicon layer 103 is preferablyaccomplished by steps outlined and described below with reference toFIGS. 2A-C

FIG. 1C shows the released silicon-based device layer 105′ coupled to anew substrate 101″ to form a solar cell 130. Prior to coupling thereleased silicon-based device layer 105′ to the new substrate 101″, thereleased silicon-based device layer 105′ and/or substrate 101″ arepreferably provided with the appropriate electrical contacts andanti-reflecting coatings to form a working solar cell 130. The releasedsingle crystal silicon wafer 101′ is reused preferably from 0-50 times,and more preferably from 20-30 times to make additional composite wafersand solar cells.

FIG. 2A shows a block flow diagram 200 outlining steps for making asolar cell. In the step 201 a composite wafer 100 is formed, such asdescribed with reference to FIG. 1A. After the composite wafer 100 isformed in the step 201, in the step 203 the sacrificial porous siliconlayer 103 is controllably or selectively etched to form a releasedsilicon-based device layer 105′ and a released single crystal siliconwafer 101′, such as shown in FIG. 1B.

Referring to FIG. 2B, the composite wafer 100 is formed using any numberof techniques or combination of techniques. For example, the sacrificialporous silicon layer 103 is deposited in the step 202 by spin coatingpoly-silicon on the substrate 101, which is preferably a single crystalsilicon wafer. The poly-silicon is then dried or cured to remove solventand form the sacrificial porous silicon layer 103. As described above,the sacrificial porous silicon layer 103 has a porosity of 30% or more,which is believed to increase the selectivity of the etch rate for thesacrificial porous silicon layer 103.

After the sacrificial porous silicon layer 103 is formed in the step202, in the step 204 the device layer 105 is formed over the sacrificialporous silicon layer 103. The device layer 105 is preferably formedusing any suitable technique, but is preferably formed by epitaxiallygrowing a crystalline or semi-crystalline silicon device layer usingvapor deposition techniques. The device layer 105 that is formed in thestep 204 is preferably a p-doped device layer. The device layer 105 isformed, for example, by vapour depositing silicon-based precursors thatincludes a p-dopant or p-dopants, herein referred to as p-dopedsilicon-based precursors. Suitable p-doped silicon-based precursorsinclude trivalent atoms typically from group IIIA of the periodic table,such as boron or aluminum. Alternatively to using p-doped silicon-basedprecursors to form the device layer 105, the device layer 105 may bedoped after its formation using ion implantation techniques. In somecases, it can be useful to form the device layer 105 by using p-dopedsilicon-based precursors, such as described above, and further dopingthe device layer 105 with the same or different dopants using ionimplantation techniques.

Now referring to FIG. 2C, in step 203 the sacrificial porous siliconlayer 103 is controllably or selectively etched to form a releasedsilicon-based device layer 105′ and a released single crystal siliconwafer 101′. In accordance with the embodiments of the invention, thesacrificial porous silicon layer 103 is controllably or selectivelyetched by first patterning the device layer 105 with access groove orholes in the step 206. After the device layer 105 is patterned withaccess grooves or holes in the step 206, the composite wafer 100 istreated with an etchant, such as described above and below. Patterningthe device layer 105 with access grooves or holes prior to treating thecomposite wafer 100 with an etchant can result in faster etch rates byallowing a greater surface area of the sacrificial poly-silicon layer103 to be initially exposed to the etchant.

In accordance with the embodiments of the invention, the device layer105 is patterned with access groves or holes in the step 206 by usingphoto-resist masking and etching techniques. It will be clear to oneskilled in the art that while patterning the device layer 105 withaccess groves or holes, such as described above, can be beneficial, itis not necessary to implement the present invention. Regardless ofwhether the step 206 of patterning the device layer 105 with accessgroves or holes is performed, in the step 208 the composite wafer 100 istreated with an etchant to form a released silicon-based device layer105′ and a release single crystal silicon wafer 101′, such as shown inFIG. 1B.

Still referring to FIG. 2C, in the step 208 the composite wafer 100 istreated with an aqueous etchant comprising one or more of potassiumhydroxide, sodium hydroxide and hydrogen fluoride in concentrations of5% or less by weight. Preferably, the aqueous etchant is maintained attemperatures in a range of 0 to 10 degrees Celsius during the step 208.This temperature range results in better selectivity during the etchingprocess. In further embodiments of the invention the aqueous etchantincludes an alcohol, such as isopropyl alcohol, in a concentration of10% or less by weight. In still further embodiments of the invention,the etchant includes a surfactant in a concentration of 1% or less byweight. Suitable surfactants include, but are not limited to:

1) Anionic Surfactants, such as, for example, Perfluorooctanoate (PFOAor PFO), Perfluorooctanesulfonate (PFOS), Sodium dodecyl sulfate (SDS),ammonium lauryl sulfate, Sodium laureth sulfate and Alkyl benzenesulfonate;2) Soap or fatty acid salt surfactants;3) Cationic Surfactants, such as, for example, Cetyl trimethylammoniumbromide (CTAB), a.k.a. hexadecyl trimethyl ammonium bromide,Cetylpyridinium chloride (CPC), Polyethoxylated tallow amine (POEA),Benzalkonium chloride (BAC) and Benzethonium chloride (BZT);4) Zwitterionic (amphoteric) Surfactants, such as, for example Dodecylbetaine, Cocamidopropyl betaine, Coco ampho glycinate; and5) Nonionic Surfactants, such as, for example Alkyl poly(ethyleneoxide), Alkylphenol poly(ethylene oxide) Copolymers of poly(ethyleneoxide) and poly(propylene oxide), Octyl glucoside, Decyl maltoside,Fatty alcohols, Cetyl alcohol, Oleyl alcohol, Cocamide MEA, cocamideDEA, Polysorbates and Dodecyl dimethylamine oxide.

In still further embodiments of the invention, during the selectiveetching step 208 the composite wafer 100 and the aqueous etchant aretreated with ultrasonic energy. After the release, silicon-based devicelayer 105′ is formed in the step 203. In the step 205 the releasedsilicon-based device layer 105′ is attached to a suitable substrate101″, such as, for example, a glass substrate, and provided with all theappropriate inter-connects to form a solar cell.

Referring now to FIG. 3, in further embodiments of the invention, asolar panel 300 is formed by attaching multiple solar cells 130, 130′and 130″, such as the solar cell described above, to a common substrate301. The solar cells 130, 130′ and 130″ are provided with all of theappropriate inter-connects 302, 302′ and 302″ to each other and/or thesubstrate 301 to allow the solar panel 300 to collect solar energy andprovide power to a device 401 such as described below.

With reference to FIG. 4, a system 400 includes a solar panel 300, suchas described above with reference to FIG. 3. The solar panel 300 iselectrically coupled to a battery or energy storage device 403 throughan electrical connection 413. The solar panel 300 and the battery orenergy storage device 403 are electrically coupled to a device 401through electrical connections 411 and 415, respectively. The device 401is configured with the appropriate circuitry, such that the solar panel300 and the battery or energy storage device is capable of powering thedevice 401. The device 401 may be computer, a hand-held communicationdevice or any other electronic device now known or later developed. Inaccordance with the embodiments of the invention, the solar panel 300and battery energy storage device 403 are built into the device 401 andthe device 401 includes a display unit, screen or user interface 405.

The present invention has been described in terms of specificembodiments incorporating details to facilitate the understanding of theprinciples of construction and operation of the invention. As such,references herein to specific embodiments and details thereof are notintended to limit the scope of the claims appended hereto. It will beapparent to those skilled in the art that modifications can be made inthe embodiments chosen for illustration without departing from thespirit and scope of the invention.

What is claimed is:
 1. A method of selectively etching a silicon wafer,the method comprising: a) providing a sacrificial porous silicon layeron a single crystal silicon wafer; and b) selectively etching thesacrificial porous silicon layer with an aqueous etchant; wherein theaqueous etchant is maintained at a temperature in a range of 0° C. to10° C. during step b) and the aqueous etchant comprises one or more ofpotassium hydroxide, sodium hydroxide and hydrogen fluoride.
 2. Themethod of claim 1, wherein the aqueous etchant includes one or more ofthe potassium hydroxide, sodium hydroxide and hydrogen fluoride in aconcentration of 5% or less by weight.
 3. The method of claim 1, whereinthe aqueous etchant further comprises a surfactant.
 4. The method ofclaim 3, wherein the surfactant is selected from the group consisting ofanionic surfactants, fatty acid surfactants, cationic surfactants,zwitterionic surfactants, and non-ionic surfactants.
 5. The method ofclaim 1, wherein the aqueous etchant comprises 1% or less by weight ofthe surfactant.
 6. The method of claim 1, wherein the aqueous etchantfurther comprises an alcohol.
 7. The method of claim 6, wherein thealcohol is isopropyl alcohol.
 8. The method of claim 1 furthercomprising subsequent to step a) and prior to step b), forming acrystalline silicon device layer on the sacrificial porous siliconlayer.
 9. The method of claim 9, wherein the crystalline silicon devicelayer is patterned with access grooves or holes sacrificial poroussilicon layer.
 10. The method of claim 10, wherein the aqueous etchantcontacts the sacrificial porous silicon layer via the access grooves orholes in the crystalline silicon device layer.
 11. The method of claim1, wherein the sacrificial porous silicon layer comprises a materialselected from the group consisting of a carbon doped oxide, aspin-on-glass (SOG) and fluoridated silicon glass (FSG).
 12. The methodof claim 8, wherein the crystalline silicon layer is a p-dopedcrystalline silicon layer.
 13. A method of selectively etching a siliconwafer, the method comprising: a) providing a sacrificial porous siliconlayer on a single crystal silicon wafer; b) forming a p-dopedcrystalline silicon device layer on the sacrificial porous siliconlayer, thereby forming a composite wafer; and c) selectively etching thesacrificial porous silicon layer with an aqueous etchant; wherein theaqueous etchant is maintained at a temperature in a range of 0° C. to10° C. during step c) and the aqueous etchant comprises a surfactant.15. The method of claim 13, wherein the aqueous etchant comprises thesurfactant in a concentration of 1% by weight or less.
 15. The method ofclaim 13, wherein the surfactant is an anionic surfactant selected fromthe group consisting of Perfluorooctanoate (PFOA or PFO),Perfluorooctanesulfonate (PFOS), Sodium dodecyl sulfate (SDS), ammoniumlauryl sulfate, Sodium laureth sulfate, and Alkyl benzene sulfonate. 16.The method of claim 13, wherein the surfactant is a cationic surfactantselected from the group consisting of Cetyltrimethylammonium bromide(CTAB), Cetylpyridinium chloride (CPC), Polyethoxylated tallow amine(POEA), Benzalkonium chloride (BAC) and Benzethonium chloride (BZT). 17.The method of claim 13, wherein the surfactant is a zwitterionicsurfactant selected from the group consisting of Dodecyl betaine,Cocamidopropyl betaine, and Coco ampho glycinate.
 18. The method ofclaim 13, wherein the surfactant is a non-ionic surfactant selected fromthe group consisting of Alkyl poly(ethylene oxide), Alkylphenolpoly(ethylene oxide) Copolymers of poly(ethylene oxide) andpoly(propylene oxide), Octyl glucoside, Decyl maltoside, Fatty alcohols,Cetyl alcohol, Oleyl alcohol, Cocamide MEA, cocamide DEA, Polysorbatesand Dodecyl dimethylamine oxide.
 19. The method of claim 13, wherein thesurfactant is a soap or a fatty acid salt.
 20. The method of claim 13further comprising during step c) treating the composite wafer andaqueous etchant to ultrasonic energy.